Bus interface circuit for controlling data transfer

ABSTRACT

A transmitter includes a transmitting buffer (21) for temporarily storing the information received from a first bus (11) of N (N is a natural number) bits width and a transmitting input distributer (22) and a transmitting output distributer (23) respectively provided in the input side and output side of the transmitting system buffer (21). A receiver includes a receiving buffer (31) for temporarily storing the information received from the second bus (12) and for sending the information to the first bus (11) and a receiving input distributer (32) and a receiving distributer (33) respectively provided in the input side and output side of the receiving buffer. The transmitting buffer (21) has at least m (m is a natural number) buffers of N bits width. When the second bus (12) has N bits width, the transmitting input distributer (22) sequentially inputs the information sent from the first bus to m buffers and the transmitting output distributer (23) sequentially extracts the information input to the buffers to send to the second bus ( 12). When the second bus (12) has mN bits width, the transmitting input distributer (22) sequentially inputs the information sent from the first bus (11) to m buffers and the transmitting output distributer (23) simultaneously extracts the information into the m buffers to send to the second bus (12).

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a bus interface circuit andparticularly to a bus interface circuit for controlling data transferbetween buses in different bit width of the address lines and datalines.

2. Description of the related Art

In a computer system having a couple of buses, a bus interface isgenerally necessary between these buses. For instance, in themultiprocessor system, a plurality of central processing units (CPU),memories, and input/output units (I/O units) which are common resourcesof these CPUs respectively provide first buses and connect these busesthrough the common second bus. In general, the first bus is called alocal bus and the second bus is called a system bus. The bus interfaceis provided, corresponding to each local bus, for connecting thecorresponding local bus to the system bus.

A computer system in these years tends to increase the amount ofinformation to be transferred (address and a series of data) in a singletransfer sequence by widening the bus width in order to improve systemperformance.

However, when bus width is widened, a number of signal lines naturallyincreases and the scale of hardware becomes large. Therefore,considering the required performance of the system, the width of secondbus (system bus) must be determined to be of N bits (for example, 32bits) or of to 2N bits (for example, 64 bits).

Thereby, it is effective for the bus interface to have the structureready for both N bits mode and 2N bits mode. The present inventionrelates to a bus interface which may be used in common for suchN-bit/2N-bit (including 3,4, . . . mN-bit) widths.

FIG. 1 is a schematic diagram of the system example to which the presentinvention is applied. In FIG. 1, a computer system 10 comprises aplurality of first buses (local bus) 11 and a second bus (system bus) 12as the buses for information transfer. The first bus 11 is connectedwith the central processing unit (CPU) 14, memory (MEM) 15 and I/O unit16.

These first bus 11 and second bus 12 are connected through bus interface(BS I/F) 13. In this case, the second bus 12 has the width, for example,of 32 (N= 32) bits but it must be expanded up to 2N (=64) bits whenimprovement of system performance is requested. Accordingly, it isconvenient that the bus interface 13 may be used in common to N bits and2N bits.

FIG. 3 is a timing chart indicating the operations in the transmittingside of the system, particularly in the side of a first bus (N bits) inthe prior art of FIG. 2. S111, S112 in FIG. 3 denote the switchingcontrol signals (selecting REG100 or REG101) applied to the selector 110of FIG. 2.

FIG. 4 is a timing chart indicating operations in the transmitting sideof the system and particularly in the side of second bus (N bits) in theprior art of FIG. 2. S121, S122 in FIG. 4 denote the switching controlsignals (selecting REG102 or buffer 21) applied to the selector 120 ofFIG. 2.

FIG. 5 is a timing chart indicating operations in the transmitting sideof the system and particularly in the side of the second bus (2N bits)in the prior art of FIG. 2. S131, S132 in FIG. 5 denote the switchingcontrol signals (selecting REG105 or REG106) applied to the selector 130in FIG. 2.

FIG. 6 is a timing chart indicating operations in the receiving side ofthe system and particularly in the side of the second bus (N bits) inthe prior art of FIG. 2. S131, S132 in FIG. 6 denote the switchingcontrol signals (selecting REG105 or REG106) applied to the selector 130in FIG. 2.

FIG. 7 is a timing chart indicating operations in the receiving side,particularly in the side of the second bus (2N bits) in the prior art ofFIG. 7.

FIG. 8 is a timing chart indicating operations in the receiving system,particularly in the side of the first bus in the prior art of FIG. 2.

According to the bus interface of the prior art, when the second bus(system bus) 12 changes to 2N bits mode (FIG. 5) from the N bits mode(FIG. 4), a problem arises that the read cycle of buffer must be reducedto a half for improvement of the operation rate.

Moreover, this problem also occurs in the receiving system. Namely, whenthe second bus (system bus) 12 changes to 2N bits mode (FIG. 7) from theN bits mode (FIG. 6), the write cycle of buffer must be reduced to ahalf for improvement of the operation rate, as will be apparent fromFIG. 6.

Such a problem results in a hardware disadvantage, in that a high speedbuffer (for example, high speed RAM) must be used. Avoidance of such adisadvantage requires that the transfer cycle of the buffer must bedoubled to lower the operation rate. Thereby, the data transfercapability must be reduced to a half; moreover such a disadvantage is inturn generated that the data processing capability of the system isreduced to a half.

SUMMARY OF THE INVENTION

It is therefore an object of the present invention to provide a basinterface circuit, considering the problems explained above in the priorart, which is capable of performing the interface function with thefirst bus (local bus) and second bus (system bus) without using a highspeed buffer even when the bus width of the second bus (system bus)changes to 2N, 3N, 4N, . . . , mN bits from N bits.

It is another object of the present invention to provide a bas interfacecircuit which performs the interface function between the first bus(local bus) and second bus (system bus) in the same transfer cycle evenwhen the bus width of the second bus (system bus) changes to 2N, 3N, 4N,. . . mN bits from N bits and also does not require any modification ofdata transfer part such as CPU, I/O unit, etc. connected to the businterface circuit.

In the bus interface circuit of the present invention, a transmitterincludes a transmitting buffer (21) for temporarily storing theinformation received from a first bus (11) of N (N is a natural number)bits width and a transmitting input distributor (22) and a transmittingoutput distributor (23) respectively provided in the input side andoutput side of the transmitting system buffer (21). A receiver includesa receiving buffer (31) for temporarily storing the information receivedfrom the second bus (12) and for sending the information to the firstbus (11) and a receiving input distributor (32) and a receivingdistributor (33) respectively provided in the input side and output sideof the receiving buffer. The transmitting buffer (21) has at least m (mis a natural number) buffers of N bits width. When the second bus (12)has N bits width, the transmitting input distributor (22) sequentiallyinputs the information sent from the first bus to m buffers and thetransmitting output distributor (23) sequentially extracts theinformation, as input to the buffers, to send same to the second bus(12). When the second bus (12) has mN bits width, the transmitting inputdistributor (22) sequentially inputs the information sent from the firstbus (11) to m buffers and the transmitting output distributor (23)simultaneously extracts the information, input into the m buffers, tosend same to the second bus (12).

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a schematic diagram indicating an example of a system to whichthe present invention is applied;

FIG. 2 is a circuit diagram indicating an example of a bus interfacecircuit of the prior art;

FIG. 3 is a timing chart indicating operations in the side oftransmitting system, particularly in the side of the first bus (N bits)in the prior art of FIG. 2;

FIG. 4 is a timing chart indicating operations in the transmitting sideof the system, particularly in the side of a second bus (N bits) in theprior art of FIG. 2;

FIG. 5 is a timing chart indicating operations in the transmitting sideof the system, particularly in the side of a second bus (2N bits) in theprior art of FIG. 2;

FIG. 6 is a timing chart indicating operations in the receiving side ofthe system, particularly in the side of a second bus (N bits) in theprior art of FIG. 2;

FIG. 7 is a timing chart indicating operations in the receiving side ofthe system, particularly in the side of a second bus (2N bits) in theprior art of FIG. 2;

FIG. 8 is a timing chart indicating operations in the receiving side ofthe system, particularly in the side of a first bus in the prior art ofFIG. 2;

FIG. 9 is a diagram indicating the basic structure of a bus interfacecircuit of the present invention;

FIG. 10 is a circuit diagram indicating an embodiment of a bus interfacecircuit of the present invention;

FIG. 11 is a timing chart indicating operations in the transmitting sideof the system, particularly in the side of the first bus in FIG. 10;

FIG. 12 is a timing chart indicating operations in the transmitting sideof the system, particularly in the side of the second bus (N bits) inFIG. 10;

FIG. 13 is a timing chart indicating operations in the transmitting sideof the system, particularly in the side of the second bus (2N bits) inFIG. 10;

FIG. 14 is a timing chart indicating operations in the receiving side ofthe system, particularly in the side of the second bus (N bits) in FIG.10;

FIG. 15 is a timing chart indicating operations in the receiving side ofthe system, particularly in the side of the second bus (2N bits) in FIG.10; and

FIG. 16 is a timing chart indicating operations in the receiving side ofthe system, particularly in the side of the first bus in FIG. 10.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

A preferred embodiment of the present invention will be explained indetail with reference to the accompanying drawings.

FIG. 9 is a diagram indicating the basic structure of a bus interfacecircuit of the present invention. In the transmitting system, atransmitting system buffer 21, a transmitting system input distributingpart 22 and a transmitting system output distributing part 23 areprovided. In the receiving system, a receiving system buffer 31, areceiving system input distributing part 32 and a receiving systemoutput distributing part 33 are provided.

In regard to the transmitting system, the transmitting system buffer 21is formed by a plurality of m buffers 41, 41' in the N bits widthconnected in series. In case the second bus 12 is formed in the N bits(for example, 32 bits) width, the transmitting system input distributingpart 22 sequentially inputs the address and a series of data sent fromthe first bus 11 to the m buffers 41, 41', while the transmitting systemoutput distributing part 23 sequentially extracts contents of these mbuffers and sends same to the second bus 12.

In case the second bus 12 is formed in the mN bits width (m×32 bits),the transmitting system input distributing part 22 sequentially inputsthe address and a series of data sent from the first bus 11 to eachbuffer, while the transmitting system output distributing part 23simultaneously extracts the contents of these m buffers 41, 41' andsends same to the second bus. The structure of this transmitting systemis also employed in the receiving system.

In regard to the receiving system, the receiving system buffer 31 isformed by cascade-connecting the receiving system buffer 31 and aplurality of m buffers 51, 51' in the N bits length. In case the secondbus 12 is formed in the N bits (for example, 32 bits) width, thereceiving system input distributing part 32 sequentially inputs theaddress and a series of data sent from the second buffer 12 to the mbuffers 51, 51' and the receiving system output distributing part 33extracts sequentially the contents of these m buffers and sends same tothe first bus 11.

Moreover, in case the second bus 12 is formed of mN bits length (m×32bits), the receiving system input distributing part 32 simultaneouslyinputs the address and a series of data sent from the second bus 12 to mbuffers and the receiving system output distributing part 33sequentially extracts the contents of these m buffers 51, 51' and sendssame to the first bus 11.

With such a structure, a single read operation suffices for a singletransfer of information.

In the prior art shown in FIG. 2, twice read operations are required fora single transfer of information. Therefore, the read operation may bereduced to a half with the structure of FIG. 9.

FIG. 10 is a diagram indicating a detailed circuit structure of the businterface circuit shown in FIG. 9. For simplification of theexplanation, the bus width of the second bus is changed to N bits or to2N bits.

In the bus interface circuit of FIG. 10, a plurality of buffer pairs 41,41' of the upper N bits and lower N bits of the 2N bits arecascade-connected as the transmitting system buffer 21. The transmittingsystem input distribution part 22 comprises the registers (REG) 200,201, 202 and selector (SEL) 210 and the transmitting system outputdistributing part 23 comprising the registers (REG) 203,204 and selector(SEL) 220.

A plurality of buffer pairs (i.e. 51, 51' of the upper N bits and lowerN bits, respectively) of the receiving buffer 31 are cascade-connected.The receiving system input distributing part 32 comprises the registers(REG) 205,206,207 and selector (SEL) 230, while the receiving systemoutput distributing part 33 comprises the registers (REG) 208, 209 andselector (SEL) 240.

Operations of this bus interface 40 will become obvious from the timingcharts shown in FIG. 11 to FIG. 16. These timing charts of FIG. 11 toFIG. 16 respectively correspond to those of FIG. 3 to FIG. 8.

FIG. 11 is a timing chart indicating operations in the transmitting sideof the system, particularly in the side of the first bus shown in FIG.10. S211, S212 in FIG. 11 are switching control signals applied to theselector 210 of FIG. 10 (selecting REG 200 or REG 202). At the risingedge of the signal S211, the contents of REG 200 are selected and at therising edge of the signal S212, the contents of REG 202 are selected.The selected contents are input to the upper N bits of buffer 41 oftransmitting system buffer 21.

Meanwhile, the contents of REG 201 are input in the lower N bits ofbuffer 41' and the transmitting system buffer 21 and these inputs arefetched to the buffer 21 by the buffer write pulse.

FIG. 12 is a timing chart indicating operations in the transmitting sideof the system, particularly to the second bus (N bits) of the businterface circuit of FIG. 10. S221, S222 in FIG. 12 are switchingcontrol signals (selecting the upper bit buffer 41 or lower bit buffer41') applied to the selector 220 of FIG. 10. At the rising edge of thesignal S221, the upper N bits buffer 41 of transmitting buffer 21 areselected and at the rising edge of the signal S222, the lower N bitsbuffer 41' of transmitting system buffer 21 are selected.

Thereby, the contents of the upper N bits and lower N bits buffers arealternately output to REG 203. In this case, the second bus 12 is in theN bits width (for example, 32 bits).

FIG. 13 is a timing chart indicating operations in the transmittingsystem, particularly to the second bus (2N bits) of the bus interfacecircuit of FIG. 10. When the second bus 12 is 2N bits (for example, 64bits), only the signal S221 becomes "1" and continues in the high level(the signal S222 becomes "0" and continues in the low level). Contentsof the upper N bits buffer 41 are transmitted to the register REG 203and simultaneously contents of lower N bits buffer 41' are transmittedto the REG 204. Moreover, contents of these registers REG 203, 204 aresimultaneously output to the second bus 12.

In FIG. 5, regarding the buffer output data, the read cycle of buffer isreduced to a half (1/2) in comparison with that in FIG. 4, realizing animprovement in operating speed. However, in FIG. 13, the read cycle ofthe buffer is similar to that of FIG. 12 and thus speed-up of the readcycle is unnecessary.

FIG. 14 is a timing chart indicating operations of the receiving system,particularly the second bus (N bits) in the bus interface circuit 40 ofFIG. 10. When the second bus 12 is N bits (for example, 32 bits) mode,the signal S231 is continuously set to the low level "0" (the signalS231 is continuously set to the high level "1") and contents (the upperN bits of second bus 12) of the register (REG) 207 are selected.Contents of REG 207 and contents (upper N bits of second bus 12) ofregister (REG) 205 are assigned alternately to the upper N bits buffer51 and lower N bits buffer 51' by the buffer write pulse. The clock ofREG 205 and the clock of REG 207 have the common frequency equal to 1/2of the basic clock and the phases thereof are shifted mutually by asmuch as one clock.

FIG. 15 is a timing chart indicating operations in the receiving system,particularly in the second bus (2N bits) in the bus interface circuit ofFIG. 10. When the second bus 12 is in the 2N bits (64 bits) mode, thesignal S231 is continuously set to the high level "1" (signal S232 iscontinuously set to the low level "0") and the contents (lower N bits ofsecond bus 12) of register (REG) 206 are selected. Contents of REG 206and contents of REG 205 (upper N bits of second bus 12) aresimultaneously fetched respectively by the upper buffer 51 and lowerbuffer 51' by the buffer write pulse.

In FIG. 7, the write cycle of the buffer is reduced to a half (1/2) incomparison with that of FIG. 6 (as shown in the column of the bufferwrite pulse), realizing an improvement in operation speed. But, in FIG.15, the write cycle of the buffer is equal to that in FIG. 14.

FIG. 16 is a timing chart indicating operations in the receiving system,particularly the first bus in the bus interface circuit of FIG. 10. InFIG. 16, S241, S242 are switching control signals applied to theselector (SEL) 240. The upper N bits buffer 51 side is selected at therising edge of S241 and the lower N bits buffer 51' side at the risingedge of S242. Therefore, the output of SEL 240 has the waveform as shownin FIG. 16. The register (REG) 209 sends a series of data D1, D2, . . .with a delay of one clock to the data line. The corresponding address isheld in the REG 208 and is then sent to the address line. REG 208latches addresses in the address enable function.

As explained above, according to an embodiment of FIG. 10, the presentinvention is flexibly applicable to the N bits mode system and 2N bitsmode system without changing the transfer cycle.

Moreover, since writing from the local bus (first bus) is carried outalternately to the upper buffer and lower buffer, even in the case ofthe N bits mode and 2N bits mode, the write speed can always be keptconstant. Read operation from the buffer is conducted simultaneously for2N bits but conducted alternately for N bits but the transfer cycle onthe bus is equal even for N bits and 2N bits. Therefore, it is no longernecessary to change the data transfer speed of the CPU, I/O unitconnected to the bus.

We claim:
 1. A bus interface circuit, comprising:a first bus having Nbits in width, where N is a natural number; a second bus; transmittingmeans comprising:a transmitting buffer having at least m sub-bufferswhere m is a natural number, each of the m sub-buffers having N bits inwidth; first input distributing means, connected to the transmittingbuffer, for receiving information including data and addresses from thefirst bus and inputting the information to the transmitting buffer, andfirst output distributing means, connected to the transmitting buffer,for receiving the information from the transmitting buffer andoutputting the information to the second bus; receiving meanscomprising:a receiving buffer; second input distributing means,connected to the receiving buffer, for receiving the information fromthe second bus and inputting the information to the receiving buffer,and second output distributing means, connected to the receiving buffer,for receiving the information from the receiving buffer and outputtingthe information to the first bus; the first input distributing meansreceiving the information from the first bus and inputting sequentiallythe information to the m sub-buffers; the first output distributingmeans, having at least first and second states, wherein each of thefirst and second states is selected by control signals indicative of thesecond bus having mN bits in width; the first state comprising thesecond bus having mN bits in width, wherein m is equal to 1.0, and thefirst output distributing means sequentially extracting the informationfrom the m transmitting buffers and sequentially transmitting theinformation to the second bus; and the second state comprising thesecond bus having mN bits in width, wherein m is not equal to 1.0, andthe first output distributing means simultaneously extracting theinformation from the m sub-buffers and simultaneously transmitting theinformation to the second bus.
 2. A bus interface circuit, comprising:afirst bus having N bits in width, where N is a natural number; a secondbus; transmitting means comprising:a transmitting buffer having an upperbuffer and a lower buffer; first input distributing means, connected tothe transmitting buffer, for receiving information from the first busand inputting the information to the transmitting buffer, and firstoutput distributing means, connected to the transmitting buffer, forreceiving the information from the transmitting buffer and outputtingthe information to the second bus; receiving means comprising:areceiving buffer; second input distributing means, connected to thereceiving buffer for receiving the information from the second bus andinputting the information to the receiving buffer, and second outputdistributing means, connected to the receiving buffer, for receiving theinformation from the receiving buffer and outputting the information tothe first bus; the first input distributing means receiving theinformation from the first bus and inputting alternately the informationto the upper buffer and lower buffer; the first output distributingmeans, having first and second states, wherein each of the first andsecond states is selected by control signals indicative of the secondbus, having a bit width; the first state comprising the second bushaving N bits in width and the first output distributing meansalternately extracting the information from the upper buffer and thelower buffer and alternately transmitting the information to the secondbus; and the second state comprising the second bus having 2N bits inwidth and the first output distributing means simultaneously extractingthe information from the upper buffer and the lower buffer andsimultaneously transmitting the information to the second bus.
 3. A businterface circuit, comprising:a first bus having N bits in width, whereN is a natural number; a second bus; transmitting means comprising:atransmitting buffer; first input distributing means, connected to thetransmitting buffer, for receiving information including addresses anddata from the first bus and inputting the information to thetransmitting buffer, and first output distributing means, connected tothe transmitting buffer, for receiving the information from thetransmitting buffer and outputting the information to the second bus;receiving means comprising:a receiving buffer having m sub-bufferswherein m is a natural number, each of the m sub-buffers having N bitsin width; second input distributing means, connected to the receivingbuffer, for receiving the information from the second bus and inputtingthe information to the receiving buffer, and second output distributingmeans, connected to the receiving buffer, for receiving the informationfrom the receiving buffer and outputting the information to the firstbus; the second input distributing means, having at least first andsecond states, wherein each of the first and second states is selectedby control signals indicative of the second bus having mN bits in width;the first state comprising the second bus having mN bits in width,wherein m is equal to 1.0, and the second input distributing meanssequentially receiving the information from the second bus andsequentially transmitting the information to m sub-buffers; the secondstate comprising the second bus having mN bits in width, wherein m isnot equal to 1.0, and the second input distributing means simultaneouslyreceiving the information from the second bus and simultaneouslytransmitting the information to m sub-buffers; and the second outputdistributing means sequentially extracting the information from the mreceiving buffers and sequentially transmitting the information to thefirst bus.
 4. A bus interface circuit, comprising:a first bus having Nbits in width, where N is a natural number; a second bus; transmittingmeans comprising:a transmitting buffer; first input distributing means,connected to the transmitting buffer, for receiving information from thefirst bus and inputting the information to the transmitting buffer, andfirst output distributing means, connected to the transmitting buffer,for receiving the information from the transmitting buffer andoutputting the information to the second bus; receiving meanscomprising:a receiving buffer having an upper buffer and a lower buffer;second input distributing means, connected to the receiving buffer, forreceiving the information from the second bus and inputting theinformation to the receiving buffer, and second output distributingmeans, connected to the receiving buffer (31), for receiving theinformation from the receiving buffer and outputting the information tothe first bus; the second input distributing means, having first andsecond states wherein each of the first and second states is selected bycontrol signals indicative of the second bus, having a bit width; thefirst state comprising the second bus having N bits in width and thesecond input distributing means alternately receiving the informationfrom the second bus and alternately transmitting the information to theupper buffer and the lower buffer; the second state comprising thesecond bus having 2N bits in width and the second input distributingmeans simultaneously inputting the information received from the secondbus and simultaneously transmitting the information to the upper bufferand the lower buffer; and the second output distributing meansalternately extracting the information from the upper buffer and lowerbuffer and transmitting the information to the first bus.